1. Technical Field
The embodiments of the invention relate to communication technology and, more particularly to receiving and managing data based on a particular communication protocol.
2. Description of Related Art
Electronic devices may employ various communication technologies to communicate. Communication links may be physical media and/or wireless links. Various communication links are known to interface at a chip level, board level, network level or at a much larger system level. Examples of communication links include buses within a digital processing device, such as a computer. Such examples include PCI (peripheral component interface) bus, ISA (industry standard architecture) bus, USB (universal serial bus), as well as other connecting media. Communication technologies are typically based on certain communicating protocols, such as SPI (system packet interface) and hypertransport (HT) based technologies. HT was also previously known as lightning data transport (LDT). The HT standard sets forth definitions for a high-speed, low-latency protocol that may interface with today's buses, such as AGP, PCI, SPI, 1394, USB2.0, and 1 Gbit Ethernet, as well as next generation buses including AGP8x, infiniband, PCI-X, PCI 3.0, and 10 Gbit Ethernet.
HT interconnects provide high-speed data links between coupled devices and most HT enabled devices include at least a pair of HT ports so that HT enabled devices may be daisy-chained. In an HT chain or fabric, a device may communicate with other coupled devices using appropriate addressing and control. Examples of devices that may be HT chained include packet data routers, server computers, data storage devices, and other computer peripheral devices. In today's networks and/or systems employing a communication link for data transfer, it is common to see HT and/or SPI (such as SPI-4) protocols being employed. The SPI-4 and HT communication standards may be utilized to transfer data between various components, devices and systems. Generally, SPI-4 and HT interconnects provide high speed data links to facilitate data transfer.
Although these communication protocols may allow for high speed data transfer, various devices receiving the data may not have the capability of processing the data at the same frequency as the data received. For example, data transfer rates of 1.6 G bits/sec may be reached utilizing HT and/or SPI-4 protocols. However, if the device receiving this data has an internal data path which runs at 400 MHz, then there is a 4-to-1 frequency scaling (may also be referred to as slow-down) relative to the input data speed. Without some mechanism to compensate and adjust for this difference in the frequencies of the input data link and the internal data path, the receiving device may not be able to adequately process the data flow.
One general technique to adequately process incoming data is to employ an internal data path that is wider than the byte-width of the incoming data stream. For example, a technique may employ an internal data path width which is the reverse ratio as the above noted ratio between the incoming data rate and the clock rate of the internal data path. Thus, for a frequency scaling of 4-to-1 between the incoming data rate and the clock frequency of the internal data path, the internal data path may be increased by a width of four to ensure that the internal data path may adequately handle the data received.
To transfer the incoming data onto an internal data path, a data receiving unit typically employs temporary storage, such as a buffer, so that the incoming data may be expanded to the width of the internal data path to retain a desired high bandwidth. When a buffer is employed to expand the data width, writes to memory of less than the width of the data path may require memories with multiple write ports. That is, in order to generate multiple writes of less than the width of the internal data path, a memory device may require more than one write port. One disadvantage of memory devices utilizing more than one write port is that the complexity of the device increases significantly. Furthermore, a specialized memory structure may be required, since many standard memory devices do not have more than one write port. The embodiments of the present invention described herewith address a situation in which a single write port and a single read port memory devices may be utilized to implement a buffer to handle the frequency scaling and data fragmentation between a high input data rate and a slower internal data path.